MAX1104EUA+【PDF 4/17 页】IC CODEC 8BIT 8-UMAX

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MAX1102/MAX1103/MAX1104

Configuring the ADC

When configuring the ADC immediately following

power-up, the first control word enables the ADC and

sets the T/H to track mode. Then wait 200s for the

internal reference to stablize (3s typical from standby

mode). Finally, the second control word sets the ADC

into either single or continuous mode and causes con-

version to take place.

Conversion Modes

The MAX1102/MAX1103/MAX1104 have two conver-

sion modes, single and continuous.

In single conversion mode (C0 = 0), a control word

must be written before an ADC conversion result can

be read, or DAC input data is accepted. Once a con-

version has occurred, the device will ignore any input

until a new control word is written. Figures 5 and 6

show the DAC and ADC single conversion mode timing

diagrams.

In continuous conversion mode (C0 = 1), the device

maintains its configuration from a single control word,

and continuously updates the ADC conversion result,

or accepts new DAC input data.

When operating the ADC and DAC simultaneously,

both converters must be in the same conversion mode.

ADC Single Conversion Mode

Set C0 = 0 to select single conversion mode. The

falling edge of SCLK after the eighth bit of each control

word causes the ADC to switch from track to hold

mode and begin conversion. To avoid corruption of the

conversion result, SCLK must be disabled for 36s

(Figure 6). After completing the conversion, the ADC

automatically returns to track mode, and the next eight

clock cycles shift out the result on DOUT.

A minimum of 3.5s in track mode is required for com-

plete acquisition.

8-Bit CODECs

______________________________________________________________________________________

SCLK

DAC

ADDR

DAC ON

DAC

ADDR

DAC ON

DAC

ADDR

DAC ON

DAC

ADDR

DAC ON

DAC

ADDR

DAC OFF

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

DIN

OUT

NOTE: "S" DENOTES THE BEGINNING OF A CONTROL WORD

Figure 5. DAC Single Conversion Mode Timing Diagram

SCLK

AIN

DOUT

MSB

tCONV

LSB

ACQUISITION MODE

ACQUISITION

MODE

MSB LSB

ADC

ADDR

ADC ON

ADC

ADDR

ADC ON

ADC

ADDR

ADC ON

ADC

ADDR

ADC ON

ADC

ADDR

ADC OFF

ADC

CONVERSION

RESULT FOR 1

CONVERSION

RESULT FOR 2

CONVERSION

RESULT FOR 3

CONVERSION

RESULT FOR 4

ADC

DIN

Figure 6. ADC Single Conversion Mode Timing Diagram

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